Journal of Interfaces, Thin Films, and Low dimensional systems

Performance investigation of an extended source germanium reconfigurable field effect transistor for advanced CMOS applications

Document Type : Original Article

Authors

Department of Electronic, Yadegar- e- Imam Khomeini (RAH) Shahr-e-Rey Branch, Islamic Azad University, Tehran, Iran

Abstract

This paper presents a comprehensive investigation into the electrical characteristics of a reconfigurable Schottky barrier transistor that utilizes germanium as the channel material and features an extended source region. The impact of critical design parameters on the device performance is thoroughly assessed. The device is capable of achieving both n-type and p-type operation on a single device by adjusting the appropriate bias for the electrodes, without the need for additional physical doping. The proposed device offers a wider tunneling area at the interface of the source and channel region, leading to an improvement in device switching performance and a reduction in the threshold voltage required for the onset of tunneling. The gate workfunction is a crucial design parameter that should be optimized to minimize the off-state current for both n-type and p-type operation. The findings reveal that the on/off current ratio of 5.26×104 and 5.9×104 can be attained for n-type and p-type operation, respectively. Furthermore, the analog performance of the device has been examined, and a cut-off frequency of fT=3GHz has been achieved for n-type and p-type device. These results provide valuable insights into the development of low-power reprogrammable logic circuits.

Keywords

Main Subjects

Article Title [Persian]

بررسی عملکرد ترانزیستور شاتکی ژرمانیومی با قابلیت پیکربندی مجدد و سورس توسعه یافته برای کاربردهای CMOS پیشرفته

Authors [Persian]

  • حمید رضا حیدری
  • زهرا آهنگری
  • حامد نعمتیان
  • کیان ابراهیم کافوری

گروه الکترونیک،واحد یادگار امام خمینی (ره) شهر ری ، دانشگاه آزاد اسلامی ، تهران، ا یرا ن

Abstract [Persian]

در این مقاله عملکرد ترانزیستور شاتکی با قابلیت پیکربندی مجدد و کانال ژرمانیومی به همراه سورس توسعه یافته به طور کامل مورد بررسی قرار گرفته است. اثر پارامترهای مهم طراحی بر عملکرد این افزاره مورد مطالعه و بررسی قرار گرفته است. این افزاره قابلیت عملکرد کانال n و کانال p را تنها با تغییر بایاس الکترودهای مربوطه دارد و نیازی به تغییر آلایش فیزیکی افزاره نیست. به دلیل بکارگیری ساختار سورس توسعه یافته، مساحت ناحیه تونل زنی در فصل مشترک سورس با کانال افزایش یافته که این مسئله منجر به بهبود خاصیت کلیدزنی افزاره و کاهش ولتاژ آستانه لازم برای شروع پدیده تونل زنی می‌گردد. تابع کار گیت یک مشخصه مهم افزاره است که برای دستیابی به کمترین جریان حالت خاموش در کانال n و کانال p لازم است مقدار بهینه ای برای آن تعیین گردد. براساس نتایج شبیه سازی، نسبت جریان روشن به خاموش 104×5.26 و 104×5.9 به ترتیب برای افزاره های کانال n و کانال p بدست آمده است. همچنین فرکانس قطع در حدود GHz 3T= f برای هر دو افزاره کانال n و کانال p محاسبه گردیده است. نتایج این مقاله چشم انداز روشنی را برای توسعه مدارهای منطقی توان پایین با قابلیت برنامه ریزی مجدد فراهم میکند.

Keywords [Persian]

  • ترانزیستور شاتکی
  • انتشار ترمویونی
  • تونل زنی مستقیم
  • ترانزیستور با قابلیت پیکربندی مجدد
[1] Aishwarya Kaity, Sangeeta Singh,  P. N. Kondekar. "Silicon-on-nothing electrostatically doped junction less tunnel field effect transistor (SON-ED-JLTFET): A short channel effect resilient design." Silicon, 13 (2021) 9-23.
[2] Nassima Bourahla, Ahmed Bourahla, Baghdad Hadri. "Comparative performance of the ultra-short channel technology for the DGFinFET characteristics using different highk dielectric materials." Indian Journal of Physics, 95 (2021) 1977-1984.
[3] Kerim Yılmaz, Ghader Darbandy, Gilles Reimbold, Benjamin Iniguez, Francois Lime, Alexander Kloes. "Equivalent DG dimensions concept for compact modeling of short-channel and thin body GAA MOSFETs including quantum confinement." IEEE Transactions on Electron Devices, 67 (2020) 5381-5387.
[4] Mile Schwarz, Laurie E. Calvet, John P. Snyder, Tillmann Krauss, Udo Schwalke, Alexander Kloes. "On the physical behavior of cryogenic IV and III–V Schottky barrier MOSFET devices." IEEE Transactions on  Electron Devices, 64 (2017) 3808-3815.
[5] Prashanth Kumar, WasimArif, Brinda Bhowmick. "Scaling of dopant segregation Schottky barrier using metal strip buried oxide MOSFET and its comparison with conventional device." Silicon, 10 (2018) 811-820.
[6] Prashanth Kumar Brinda Bhowmick. "Sourcedrain junction engineering Schottky barrier MOSFETs and their mixed mode application." Silicon, 12 (2020) 821-830.
[7] Amit Saxena, Manoj Kumar, R. K. Sharma, and R. S. Gupta. "SOI Schottky barrier nanowire MOSFET with reduced ambipolarity and enhanced electrostatic integrity." Journal of Electronic Materials 49 (2020) 4450-4456.
[8] Bin Sun, Benjamin Richstein, Patrick Liebisch, Thorben Frahm, Stefan Scholz, Jens Trommer, Thomas Mikolajick, and Joachim Knoch. "On the operation modes of dualgate reconfigurable nanowire transistors." IEEE Transactions on Electron Devices, 68 (2021) 3684-3689.
[9] Christian Roemer, Ghader Darbandy, Mike Schwarz, Jens Trommer, André Heinzig, Thomas Mikolajick, Walter M. Weber, Benjamín Iñíguez, Alexander Kloes. "Physics-based dc compact modeling of schottky barrier and reconfigurable fieldeffect transistors." IEEE Journal of the Electron Devices Society, 10 (2021) 416- 423.
[10] C. Navarro, S. Barraud, S. Martinie, J. Lacord, M. A. Jaud, M. Vinet. "Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations." Solid-State Electronics, 128 (2017) 155-162.
[11] Yan Yao, Yabin Sun, Xiaojin Li, Yanling Shi, Ziyu Liu. "Novel reconfigurable field-effect transistor with asymmetric spacer engineering at drain side." IEEE Transactions on Electron Devices, 67 (2020) 751-757.
[12] Jong-Ho Bae, Hyeongsu Kim, Dongseok Kwon, Suhwan Lim, Sung-Tae Lee, ByungGook Park, Jong-Ho Lee. "Reconfigurable field-effect transistor as a synaptic device for XNOR binary neural network." IEEE Electron Device Letters, 40 (2019) 624-627.
[13] Daehoon Wee, Hui Tae Kwon, Won Joo Lee, Hyun-Seok Choi, Yu Jeong Park, Boram Kim, Yoon Kim. "U-shaped Reconfigurable Field-effect Transistor." Journal of Semiconductor Technology and Science 19 (2019): 63-68.
[14] André Heinzig, Stefan Slesazeck, Franz Kreupl, Thomas Mikolajick, Walter M. Weber. "Reconfigurable silicon nanowire transistors." Nano letters, 12 (2012) 119- 124.
[15] Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. "Dual-thresholdvoltage configurable circuits with threeindependent-gate silicon nanowire FETs." In 2013 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2111- 2114. IEEE, 2013.
[16] Tillmann Adrian Krauss, Frank Wessely, Udo Schwalke. "Favorable combination of Schottky barrier and junctionless properties in field-effect transistors for high temperature applications." ECS Transactions, 75 (2016) 57.
[17] Wenwen Fei, Jens Trommer, Max Christian Lemme, Thomas Mikolajick, André Heinzig. "Emerging reconfigurable electronic devices based on two‐ dimensional materials: A review." InfoMat, 4 (2022) e12355.
[18] Yue Zhou, Yasai Wang, Fuwei Zhuge,  Jianmiao Guo, Sijie Ma, Jingli Wang, Zijian Tang et al., "A Reconfigurable Two‐WSe2‐ Transistor Synaptic Cell for Reinforcement Learning." Advanced Materials, 34 (2022) 2107754.
[19] Yoshitaka Shingaya, Amir Zulkefli, Takuya Iwasaki, Ryoma Hayakawa, Shu Nakaharai, Kenji Watanabe, Takashi Taniguchi, Yutaka Wakayama. "Dual‐Gate Anti‐Ambipolar Transistor with Van der Waals ReS2/WSe2 Heterojunction for Reconfigurable Logic Operations." Advanced Electronic Materials 9 (2023) 2200704.
[20] ATLAS User Manual, Santa Clara, USA: Silvaco International, (2015). 
Journal of Interfaces, Thin Films, and Low dimensional systems
Volume 7, Issue 1
December 2023
Pages 675-684